Occupancy Math on the AMD MI355X: A From-First-Principles Guide
The article presents a from-first-principles guide to calculating occupancy on AMD's MI355X GPU, explaining how to derive theoretical occupancy using key hardware limits like wavefront size, shared memory, and register file constraints. It demonstrates the step-by-step math behind occupancy estimation for kernel optimization on AMD CDNA4 architecture.
Background
- The AMD MI355X is a next-generation data-center GPU for AI and HPC workloads, expected to ship in the second half of 2025. It succeeds the MI300X and is built on a more advanced manufacturing process (3nm vs 5/6nm).
- "Occupancy" is a key GPU performance concept: it measures how many of a GPU's available compute threads are actively running at once. Higher occupancy helps hide memory latency but can limit per-thread resources like registers and shared memory.
- The article walks through step-by-step math to compute occupancy for the MI355X, using its hardware specs (number of compute units, registers, shared memory, wavefront size) and typical kernel constraints. This is the kind of low-level performance analysis that kernel engineers and system designers do when optimizing AI or scientific code for a new architecture.
- AMD's CDNA architecture (used in the MI300X and MI355X) is optimized for matrix math common in deep learning, competing directly with NVIDIA's H100/B200 GPUs. Understanding occupancy trade-offs helps developers decide how to tune their kernels for maximum throughput.