Occupancy Math on the AMD MI355X: A From-First-Principles Guide
The article explains how to calculate occupancy for the AMD MI355X GPU from first principles, covering its compute unit architecture, wavefront scheduling, and register/shared memory constraints to guide optimization of kernel occupancy.
Background
- The AMD MI355X is a next-generation AI accelerator (GPU) that AMD has announced but not yet fully shipped; it is designed to compete with NVIDIA's H100/B200 data-center GPUs for training and running large language models (LLMs).
- "Occupancy" is GPU performance jargon: it measures how many of a chip's parallel computational threads/units are kept busy at any given moment. Low occupancy means the hardware is underutilized; high occupancy means more of the chip's potential is being used.
- This blog post walks through the first-principles math to figure out the MI355X's occupancy limits — i.e., what prevents it from running at full speed — using its hardware specs (number of compute units, cache sizes, register file, etc.). It is written by an independent engineer who reverse-engineers these numbers from official AMD documents.
- Such analysis matters because AI companies buying billions of dollars' worth of these chips want to know whether AMD's architecture can actually deliver on its paper specifications in real workloads, especially compared to NVIDIA's dominant ecosystem.