Occupancy Math on the AMD MI355X
The article analyzes the occupancy math and compute throughput for the AMD MI355X GPU, examining how its architectural features like shared memory, register file size, and wavefront scheduling affect kernel occupancy limits and overall performance.
Background
AMD's MI355X is a next-generation GPU accelerator for AI and HPC workloads, competing with Nvidia's B200 "Blackwell" and H100. The blog post walks through "occupancy math" — a low-level optimization technique that calculates how many threads (wavefronts) a GPU can keep active simultaneously versus how many its compute units can physically hold. High occupancy can hide memory latency but may limit per-thread performance due to limited register/SRAM resources. The author profiles the MI355X's specs (CU count, register file size, shared memory per compute unit) and models different kernel configurations. For readers in the AI/ML hardware space, these details matter because AMD is pushing its MI300X and upcoming MI350 series as viable alternatives to Nvidia's dominant lineup, and actual programming-level characteristics (not just peak TFLOPS) determine real-world throughput for deep-learning training and inference.