Occupancy Math on the AMD MI355X: A From-First-Principles Guide
The article provides a detailed, first-principles breakdown of occupancy calculation on AMD's MI355X GPU, explaining how to compute thread block occupancy based on hardware limits like shared memory, registers, and workgroup size to optimize kernel performance.
Background
- AMD's MI355X is a next-generation data-center GPU designed for AI and scientific computing, expected around 2025–2026. It competes directly with Nvidia's (NVDA) B200 "Blackwell" GPUs.
- "Occupancy" is a key GPU performance concept: it measures how many of a chip's available compute threads are actively running at once, hiding memory latency. Low occupancy can leave a GPU's math units idle.
- This post reverse-engineers the MI355X's internal hardware limits (registers, shared memory, wavefront size) from AMD's published specs, then mathematically derives the occupancy for various AI workloads — a technique known as "occupancy math."
- The article is significant because the MI355X is still mostly unannounced; developers rely on leaked specs and first-principles calculations to tune their software before hardware is available. Understanding occupancy is critical for getting good performance on AMD's ROCm software stack, which lags behind Nvidia's CUDA in maturity.