Future Transistor Stacking Plans Start to Diverge IBM, Intel, Samsung, and TSMC
IBM, Intel, Samsung, and TSMC are developing diverging approaches to stacking transistors for future chip designs, moving beyond traditional planar scaling to continue performance gains. Each company is pursuing different methods for 3D transistor stacking, indicating that the semiconductor industry's roadmap is fragmenting as physical limits of current technologies approach.
Background
- The "CFET" (complementary FET) is a next-generation transistor design where n-type and p-type transistors are stacked vertically on top of each other, rather than placed side-by-side. This saves chip area and could extend Moore's Law beyond what current architectures allow.
- IBM, Intel, Samsung, and TSMC are the four key players in advanced semiconductor manufacturing. They all agree CFETs are the future, but they disagree on exactly how to build them — particularly on whether to use "forksheet" designs as an intermediate step before full stacking.
- This divergence matters because whichever approach wins will shape the entire global chip supply chain for years to come. The decisions are being made now, even though CFETs likely won't appear in commercial chips until the 2028–2032 timeframe.
- Prior context: The industry has used FinFET transistors since around 2011, and is currently transitioning to "gate-all-around" (GAA) nanosheet FETs. CFETs are the next step after GAA, but the path to get there is not agreed upon — and each company's choice affects their tooling, design rules, and partnerships.