Show HN: FPGA design acceleration – idiomatic Python to synthesizable Verilog
Holoso is a new open-source HLS tool that translates idiomatic Python into synthesizable Verilog for FPGAs. It is vendor-agnostic (supports Lattice ECP5) and handles floating-point operations, targeting applications like Kalman filters and PID controllers, addressing shortcomings the author found in existing Python-based HLS solutions.
Background
- **FPGA** (Field-Programmable Gate Array): a chip whose logic circuits can be reconfigured after manufacturing, used for high-speed, low-latency tasks like sensor fusion or control loops. **ECP5** is a specific mid-range FPGA from Lattice Semiconductor.