Examining circuit boards from the Space Shuttle's I/O Processor
The Space Shuttle's I/O Processor (IOP) used a barrel processor architecture with 25 virtual processors and two instruction sets to handle 24 data bus networks. Circuit boards from the IOP show custom Motorola chips for Manchester encoding, hybrid analog modules, and fusible-link PROM chips storing microcode.
Background
- The Space Shuttle's five general-purpose computers (IBM AP-101B) were designed before microprocessors existed. Each CPU executed ~420,000 instructions/second — weaker than a modern calculator — using dozens of simple chips and magnetic core memory.
- Each computer had two boxes: a CPU and an I/O Processor (IOP). The IOP was a separate programmable computer that handled all data flow between the CPU and the Shuttle's sensors, displays, and engines across 24 high-speed networks.
- The IOP used an unusual "barrel processor" design: it ran 25 virtual processors (with two different instruction sets) on one physical processor, switching between them every clock cycle so no network port could hog resources.
- The article's author obtained two circuit boards ("pages") from a salvaged IOP: a network interface card (using Manchester encoding, invented in the 1940s) and a PROM card holding microcode in fusible-link chips programmed by literally blowing tiny fuses.