Occupancy Math on the AMD MI355X GPU (CDNA4): A From-First-Principles Guide
A first-principles guide to calculating occupancy on the AMD MI355X GPU (CDNA4), covering hardware constraints like compute units, shared memory, registers, and wavefront limits, with examples and the occupancy calculator tool.
Background
AMD's MI355X is a data-center GPU based on the new CDNA4 architecture, competing directly with Nvidia's H100/B100 in AI and high-performance computing (HPC). "Occupancy" is a key performance concept: it measures how many parallel thread groups (wavefronts) a GPU can keep active simultaneously, which determines how well it hides memory latency. This guide walks through the math from scratch because CDNA4 introduces significant changes — larger matrix units, new memory hierarchy, and different compute unit organization — meaning developers can't rely on rules of thumb from older AMD GPUs (MI250, MI300) or Nvidia's CUDA. Understanding occupancy helps engineers tune AI training/inference kernels and scientific simulations for maximum throughput. The post is written by AMD's GPU compute team as official developer documentation.